(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of avoiding a buried contact trench at the edge of a shallow trench isolation (STI) region in the fabrication of integrated circuit devices.
(2) Description of the Prior Art
As device dimensions increase in order to permit higher device density, improved performance, and lower cost of integrated circuits, there is a growing demand for more effective isolation technology. LOCal Oxidation of Silicon (LOCOS) has been widely used in the art for forming isolation regions to insulate one active region from another. Due to encroachment such as "bird's beak" that occurs in LOCOS applications, shallow trench isolation (STI) has come into widespread use. However, the design rule for the extension of the active region to the field isolation becomes smaller for STI; for example, less than 0.1 micron for the 0.25 micron design rule. Thus, if mask misalignment occurs during the buried contact etching process, an uncontrollable leakage current may be induced since the STI trench provides a leakage path.
FIG. 1 illustrates an integrated circuit device of the prior art. A shallow trench isolation region 12 has been formed in a semiconductor substrate 10. A gate electrode 15 has been formed on the surface of the substrate. A contact 33 is to be made through the insulating layer 31 to the buried contact 27. If the mask for etching the opening through the insulating layer is misaligned, a portion of the STI 12 will be etched into. The conducting material 33 will be deposited within the opening and within the etched out portion of the trench, causing a leakage path 35, resulting in device failure.
U.S. Pat. No. 5,433,794 to Fazan et al teaches the use of silicon oxide spacers on the upper sides of a STI region. However, silicon oxide spacers will not prevent the formation of a buried contact trench within the STI region. U.S. Pat. No. 5,521,422 to Mandelman et al teach silicon nitride spacers on the upper edges of a STI region. However, the width of the spacers is not easily controlled. If the STI region is very small, the spacers may fill the STI opening preventing the etching of a trench. U.S. Pat. No. 5,506,168 to Morita et al also teaches silicon nitride spacers on the upper sides of STI regions. These spacers encroach into the active device area decreasing device density. U.S. Pat. No. 5,672,538 to Liaw et al teaches an oxide spacer on a field oxide region to smooth out the bird's head and bird's neck areas. U.S. Pat. No. 4,238,278 to Antipov teaches a method of forming both deep and shallow trenches. The paper "A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs," by Fazan et al, IEDM 93, c. 1993 by IEEE, pp. 57-60, discloses the use of oxide spacers to smooth the corners of STI regions and to reduce junction leakage by forming sloped trenches and vertical B field implants. None of these patents fully solve the problem of a leakage path through an STI trench.